Phase frequency detectors (PFDs) are digital circuits that can measure the difference in phase between two periodic signals. PFDs can be designed for the operation of synchronous logic on integrated circuits. For example, phase locked loops (PLLs) can include PFDs that generate stable clock signals and are responsible for controlling the timing and operation of entire chips. However, common PFD design architectures suffer from performance limitations. The performance limitations can include low resolution, dead zones, narrow input range, simultaneous up signal and down signal outputs, non-linear output pulse width response, low operating frequency, and an inability to drive high-capacitive loads. Accordingly, a need exists for alternative PFDs.